1. Field of the Invention
The present invention relates to a semiconductor circuit design method.
2. Related Art
Gated clock is a technique conventionally used to save power consumption of a flip-flop or a clock tree. Further, development of a conditional clocking flip-flop (CCK-F/F) and a conditional data mapping flip-flop (CDM-F/F) is underway to save power consumption of the flip-flop itself. The CCK-F/F or the CDM-F/F is normally referred to as “low power F/F” because of lower power consumption than that of an normal flip-flop.
By simple combination of the gated clock and the low power flip-flop, a clock signal is gated and the supply frequency of a clock pulse, therefore, becomes lower. Due to this, even if the low power flip-flop is used, the effect of saving the power consumption is small. Moreover, the low power flip-flop includes exclusive-OR gates or exclusive-NOR gates that are not included in the normal flip-flop, so that the low power flip-flop has a larger cell area. Therefore, if the normal flip-flop is replaced by the low power flip-flop, the cell area disadvantageously increases. That is, if the gated clock and the low power flip-flop are simply combined, the effect of cutting power consumption is not as great as expected while the cell area increases.
Moreover, according to the gated clock, if a gate receiving an enable signal and a clock signal is placed to be away from the flip-flop, then a clock delay time increases and the power consumption for charging or discharging clock wirings increases. In this case, it is preferable to directly transmit the clock signal to the flip-flop rather than to use clock gating with views of saving the power consumption and reducing the clock delay time.
Nevertheless, with a conventional semiconductor circuit design method, it is disadvantageously difficult to set a semiconductor circuit capable of reducing both the power consumption and the clock delay time while using the gated clock and the low power flip-flops.